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ISL8499
Data Sheet February 5, 2008 FN6111.3
Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Quad SPDT (Dual DPDT) Analog Switch
The Intersil ISL8499 device is a low ON-Resistance, low voltage, bidirectional, Quad SPDT (Dual DPDT) analog switch designed to operate from a single +1.65V to +4.5V supply. Targeted applications include battery powered equipment that benefit from low rON (0.24) and fast switching speeds (tON = 15ns, tOFF = 13ns). The digital logic input is 1.8V logic-compatible when using a single +3V supply. With a supply voltage of 4.2V and logic high voltage of 2.85V at both logic inputs, the part draws only 10A max of ICC current. Cell phones, for example, often face ASIC functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This part may be used to "mux-in" additional functionality while reducing ASIC design risk. The ISL8499 is offered in small form factor packages, alleviating board space limitations. The ISL8499 consists of four SPDT switches. It is configured as a dual double-pole/double-throw (DPDT) device with two logic control inputs that control two SPDT switches each. The configuration can be used as a dual differential 2-to-1 multiplexer/demultiplexer. The ISL8499 is pin compatible with the STG3699 and DG2799.
TABLE 1. FEATURES AT A GLANCE Number of Switches SW 4.3V rON 4.3V tON/tOFF 3.0V rON 3.0V tON/tOFF 1.8V rON 1.8V tON/tOFF Packages ISL8499 4 Quad SPDT (Dual DPDT) 0.24 15ns/13ns 0.26 21ns/17ns 0.45 51ns/43ns 16 Ld 3x3 TQFN, 16 Ld 3x3 QFN, 16 Ld TSSOP
Features
* Drop in Replacement for the STG3699 and DG2799 * ON-Resistance (rON) - V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.24 - V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.26 - V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.45 * rON Matching between Channels . . . . . . . . . . . . . . . . . 0.04 * rON Flatness Across Signal Range . . . . . . . . . . . . . . . 0.05 * Single Supply Operation . . . . . . . . . . . . . . . +1.65V to +4.5V * Low Power Consumption (PD) . . . . . . . . . . . . . . . . . <0.2W * Fast Switching Action (V+ = +4.3V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13ns * Guaranteed Break-Before-Make * 1.8V Logic Compatible (+3V supply) * Low ICC Current when VinH is not at the V+ Rail * Available in 16 Ld 3x3 TQFN, 16 Ld 3x3 QFN and 16 Ld TSSOP * ESD HBM Rating - COM Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9kV - All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV * Pb-Free Available (RoHS Compliant)
Applications
* Battery Powered, Handheld, and Portable Equipment - Cellular/Mobile Phones - Pagers - Laptops, Notebooks, Palmtops * Portable Test and Measurement * Medical Equipment * Audio and Video Switching
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Application Note AN557 "Recommended Test Procedures for Analog Switches"
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL8499 Pinouts
(Note 1) ISL8499 (16 LD QFN TSSOP) TOP VIEW
Ordering Information
PART PART NUMBER MARKING ISL8499IR 499I 499I 8499 IV 8499 IV 499Z 499Z TEMP. RANGE (C) PACKAGE PKG. DWG. # L16.3x3 L16.3x3 M16.173 M16.173 L16.3x3 L16.3x3
-40 to +85 16 Ld 3x3 QFN -40 to +85 16 Ld 3x3 QFN Tape and Reel -40 to +85 16 Ld TSSOP -40 to +85 16 Ld TSSOP Tape and Reel -40 to +85 16 Ld 3x3 QFN (Pb-free) -40 to +85 16 Ld 3x3 QFN Tape and Reel (Pb-free) -40 to +85 16 Ld TSSOP (Pb-free) -40 to +85 16 Ld TSSOP Tape and Reel (Pb-free)
NO1 1 COM1 2 NC1 3 IN1-2 4 NO2 5 COM2 6 NC2 7 GND 8
16 V+ 15 NC4 14 COM4 13 NO4 12 IN3-4 11 NC3 10 COM3 9 NO3
ISL8499IR-T* ISL8499IV ISL8499IV-T* ISL8499IRZ (Note) ISL8499IRZ-T* (Note) ISL8499IVZ (Note) ISL8499IVZ-T* (Note) ISL8499IRTZ (Note)
ISL8499 (16 LD 3X3 TQFN, 3X3 QFN) TOP VIEW
COM1 NO1 NC4 V+
8499 IVZ 8499 IVZ
M16.173 M16.173
16 NC1 IN1-2 NO2 COM2 1 2 3 4 5 NC2
15
14
13 12 COM4 11 NO4 10 IN3-4
99TZ
-40 to +85 16 Ld 3x3 TQFN L16.3x3A (Pb-free) -40 to +85 16 Ld 3x3 TQFN L16.3x3A Tape and Reel (Pb-free)
ISL8499IRTZ-T* 99TZ (Note)
*Please refer to TB347 for details on reel specifications
9 6 GND 7 NO3 8 COM3 NC3
NOTE: 1. Switches Shown for Logic "0" Input.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Truth Table
LOGIC 0 1 NOTE: NC SW ON OFF NO SW OFF ON
Logic "0" 0.5V. Logic "1" 1.4V with a 3V supply.
Pin Descriptions
PIN V+ GND IN COM NO NC FUNCTION System Power Supply Input (+1.65V to +4.5V) Ground Connection Digital Control Input Analog Switch Common Pin Analog Switch Normally Open Pin Analog Switch Normally Closed Pin
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ISL8499
Absolute Maximum Ratings
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V Input Voltages NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Output Voltages COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . 300mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 500mA ESD Ratings: HBM COMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>9kV HBM NOX, NCX, INX, V+, GND . . . . . . . . . . . . . . . . . . . . . . .>4kV MM COMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V MM NOX, NCX, INX, V+, GND . . . . . . . . . . . . . . . . . . . . . . .>300V CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kV
Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) JC (C/W) TQFN and QFN Package (Notes 4, 5) . 70 10 TSSOP Package (Note 3) . . . . . . . . . . 150 N/A Maximum Junction Temperature (Plastic Package). . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range ISL8499IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 6), Unless Otherwise Specified TEST CONDITIONS TEMP (C) MIN (Notes 7, 8) TYP MAX (Notes 7, 8) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON
Full V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+, (See Figure 5) V+ = 3.9V, ICOM = 100mA, VNO or VNC = Voltage at max rON,(Note 11) V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+, (Note 9) V+ = 4.5V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V 25 Full 25 Full 25 Full 25 Full V+ = 4.5V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V, or Floating 25 Full
0 -50 -150 -50 -150
0.25 0.28 0.04 0.05 0.05 0.05 -
V+ 50 150 50 150
V nA nA nA nA
rON Matching Between Channels,
rON
rON Flatness, RFLAT(ON)
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50, CL = 35pF, (See Figure 1, Note 10) V+ = 3.9V, VNO or VNC = 3.0V, RL = 50, CL = 35pF, (See Figure 1, Note 10) V+ = 4.5V, VNO or VNC = 3.0V, RL = 50, CL = 35pF, (See Figure 3, Note 10) CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 4) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 6)
25 Full 25 Full Full 25 25 25
2 -
15 13 3 -120 68 -98
25 30 23 28 -
ns ns ns ns ns pC dB dB
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel)
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ISL8499
Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 6), Unless Otherwise Specified (Continued) TEST CONDITIONS f = 20Hz to 20kHz, VCOM = 2VPP, RL = 600 TEMP (C) 25 25 25 MIN (Notes 7, 8) TYP 0.003 106 212 MAX (Notes 7, 8) UNITS % pF pF
PARAMETER Total Harmonic Distortion
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = +4.5V, VIN = 0V or V+ Full 25 Full Positive Supply Current, I+ V+ = +4.2V, VIN = 2.85V 25 1.65 4.5 0.09 1.4 12 V A A A
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL NOTES: 6. VIN = input voltage to perform proper function. 7. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 8. Parts are 100% tested at +25C. Over-temperature limits established by characterization and are not production tested. 9. Flatness is defined as the difference between maximum and minimum value of ON-Resistance over the specified analog signal range. 10. Limits established by characterization and are not production tested. 11. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value, between NC1 and NC2, NC3 and NC4 or between NO1 and NO2, NO3 and NO4. V+ = 4.5V, VIN = 0V or V+, (Note 10) Full Full Full 1.6 -0.5 0.5 0.5 V V A
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 6), Unless Otherwise Specified TEST CONDITIONS TEMP (C) MIN (Notes 7, 8) TYP MAX (Notes 7, 8) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON
Full V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, (See Figure 5) V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at max rON, (Note 11) V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, (Note 9) V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V 25 Full 25 Full 25 Full 25 Full V+ = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V, or Floating 25 Full
0 -
0.3 0.04 0.06 1.2 13 1 35
V+ 0.45 0.6 0.08 0.09 0.15 0.15 -
V nA nA nA nA
rON Matching Between Channels, rON rON Flatness, rFLAT(ON)
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 10) V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 10) V+ = 3.3V, VNO or VNC = 1.5V, RL = 50, CL = 35pF, (See Figure 3, Note 10)
25 Full 25 Full Full
2
21 17 3
30 35 27 32 -
ns ns ns ns ns
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD
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FN6111.3 February 5, 2008
ISL8499
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 6), Unless Otherwise Specified (Continued) TEST CONDITIONS CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 4) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 6) f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600 TEMP (C) 25 25 25 25 25 25 MIN (Notes 7, 8) TYP -82 68 -98 0.003 106 212 MAX (Notes 7, 8) UNITS pC dB dB % pF pF
PARAMETER Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel) Total Harmonic Distortion
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 3.6V, VIN = 0V or V+ 25 Full DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 3.6V, VIN = 0V or V+ (Note 10) Full Full Full 1.4 -0.5 0.5 0.5 V V A 0.025 0.715 A A
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 6), Unless Otherwise Specified TEST CONDITIONS TEMP (C) MIN (Notes 7, 8) TYP MAX (Notes 7, 8) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON
Full V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+, (See Figure 5) 25 Full
0 -
0.45 -
V+ 0.8 0.85
V
DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 1.65V, VNO or VNC = 1.0V, RL = 50, CL = 35pF, (See Figure 1, Note 10) V+ = 1.65V, VNO or VNC = 1.0V, RL = 50, CL = 35pF, (See Figure 1, Note 10) V+ = 2.0V, VNO or VNC = 1.0V, RL = 50, CL = 35pF, (See Figure 3, Note 10) CL = 1.0nF, VG = 0V, RG = 0, See Figure 2 RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 4) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 6) 25 Full 25 Full Full 25 25 25 25 25 3 51 43 8 -44 68 -98 106 212 65 70 58 65 ns ns ns ns ns pC dB dB pF pF
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel)
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 2.0V, VIN = 0V or V+ (Note 10) Full Full Full 1.0 -0.5 0.4 0.5 V V A
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ISL8499 Test Circuits and Waveforms
V+ LOGIC INPUT 50% 0V tOFF SWITCH INPUT VNO 90% SWITCH OUTPUT 0V tON SWITCH INPUT VOUT 90% LOGIC INPUT NO or NC COM IN GND RL 50 CL 35pF VOUT tr < 5ns tf < 5ns V+ C
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) --------------------------R L + r ( ON ) FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES
V+
C
SWITCH OUTPUT VOUT
VOUT
RG
NO or NC
COM
VOUT
V+ LOGIC INPUT ON OFF 0V Q = VOUT x CL LOGIC INPUT ON VG GND IN CL
FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION
FIGURE 2B. TEST CIRCUIT
V+
C
V+ LOGIC INPUT 0V VNX
NO
COM
NC
VOUT RL 50 CL 35pF
IN SWITCH OUTPUT VOUT 90% 0V tD LOGIC INPUT GND
CL includes fixture and stray capacitance. FIGURE 3A. MEASUREMENT POINTS FIGURE 3. BREAK-BEFORE-MAKE TIME FIGURE 3B. TEST CIRCUIT
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ISL8499 Test Circuits and Waveforms (Continued)
V+ C SIGNAL GENERATOR V+ C
rON = V1/100mA
NO or NC NO or NC
VNX IN 0V or V+ 100mA V1 IN 0V or V+
ANALYZER RL
COM
COM
GND
GND
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. rON TEST CIRCUIT
V+ C V+ C SIGNAL GENERATOR
NO or NC COM
50
NO or NC
IN1 0V or V+ IMPEDANCE ANALYZER
COM NC or NO COM
IN
0V or V+
ANALYZER RL
GND
N.C.
GND
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL8499 is a bidirectional, quad single pole/double throw (SPDT) analog switch that offers precise switching capability from a single 1.65V to 4.5V supply with low on-resistance (0.24) and high speed operation (tON = 15ns, tOFF = 13ns). The device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.65V), low power consumption (2.7W max), low leakage currents (150nA max), and the tiny TQFN, QFN and TSSOP packages. The ultra low ON-Resistance and rON flatness provide very low insertion loss and distortion to applications that require signal reproduction.
ESD protection diodes from the pin to V+ and to GND (see Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low rON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These
FN6111.3 February 5, 2008
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain 7
ISL8499
additional diodes limit the analog signal from 1V below V+ to 1V above GND. The low leakage current performance is unaffected by this approach, but the switch signal range is reduced and the resistance may increase, especially at low supply voltages. time minimizes power dissipation. The ISL8499 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0V to V+). For example driving the device with 2.85V logic (0V to 2.85V) while operating with a 4.2V supply the device draws only 6A of current (see Figure 21 for VIN = 2.85V).
OPTIONAL PROTECTION DIODE V+ OPTIONAL PROTECTION RESISTOR INX VNO or NC VCOM
High-Frequency Performance
In 50 systems, the signal response is reasonably flat even past 30MHz with a -3dB bandwidth of 104MHz (see Figure 17). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch's input to its output. Off Isolation is the resistance to this feedthrough, while Crosstalk indicates the amount of feedthrough from one switch to another. Figure 18 details the high Off Isolation and Crosstalk rejection provided by this part. At 100kHz, Off Isolation is about 68dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance.
GND OPTIONAL PROTECTION DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL8499 construction is typical of most single supply CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL8499 4.7V maximum supply voltage provides plenty of room for the 10% tolerance of 4.3V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.65V but will operate with a supply voltage below 1.5V. It is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. Refer to the "Electrical Specification" tables starting on page 3 and "Typical Performance" curves starting on page 6 for details. V+ and GND also power the internal logic and level shiftiers. The level shiftiers convert the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration.
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2.7V to 4.5V (see Figure 14). At 2.7V the VIL level is about 0.52V. This is still above the 1.8V CMOS guaranteed low output maximum level of 0.5V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition 8
FN6111.3 February 5, 2008
ISL8499 Typical Performance Curves TA = +25C, Unless Otherwise Specified
0.45 ICOM = 100mA 0.40 V+ = 1.8V 0.35 rON () rON () 0.24 0.22 0.2 +25C 0.18 V+ = 3V 0.20 V+ = 3.6V 0.15 0 1 2 VCOM (V) 3 4 5 0.14 0 1 2 VCOM (V) V+ = 4.3V 0.16 -40C 3 4 5 +85C 0.26 0.28 V+ = 4.3V ICOM = 100mA
0.30 V+ = 2.7V 0.25
FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
0.35 V+ = 2.7V ICOM = 100mA
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
0.50 V+ = 1.8V ICOM = 100mA 0.45 +85C
0.30 +85C rON () 0.25 +25C rON () 0.40
0.35
0.30 0.20 -40C 0.25 -40C
+25C
0.15 0 0.5 1.0 1.5 VCOM (V) 2.0 2.5 3.0
0.20 0 0.5 1.0 VCOM (V) 1.5 2.0
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
50
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
1.1 1.0
0 VINH AND VINL (V) V+ = 1.8V Q (pC) V+ = 3V -50
0.9 VINH 0.8 0.7 0.6 0.5 0.4 VINL
-100
-150 0 0.5 1.0 1.5 VCOM (V) 2.0 2.5 3.0
0.3 1.5 2.0 2.5 3.0 V+ (V) 3.5 4.0 4.5
FIGURE 13. CHARGE INJECTION vs SWITCH VOLTAGE
FIGURE 14. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FN6111.3 February 5, 2008
9
ISL8499 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
200 200
150
150
tON (ns)
100
tOFF (ns)
+85C +25C -40C
100
+85C +25C
50
50
-40C
0 1 1.5 2.0 2.5 3.0 V+ (V) 3.5 4.0 4.5
0 1 1.5 2.0 2.5 3.0 3.5 4.0 4.5 V+ (V)
FIGURE 15. TURN - ON TIME vs SUPPLY VOLTAGE
FIGURE 16. TURN - OFF TIME vs SUPPLY VOLTAGE
NORMALIZED GAIN (dB)
-10 V+ = 3V 0 -20 CROSSTALK (dB) GAIN -30 -40 -50 -60 ISOLATION -70 -80 -90 -100 -110 1k 10k 100k 1M 10M FREQUENCY (Hz) CROSSTALK V+ = 3V -20
10 20 30 OFF ISOLATION (dB) 5 40 50 60 70 80 90 100 110 100M 500M
PHASE
0 20 40 60 80 PHASE ()
RL = 50 VIN = 0.2VP-P to 2VP-P 1M 10M 100M FREQUENCY (Hz)
100 600M
FIGURE 17. FREQUENCY RESPONSE
FIGURE 18. CROSSTALK AND OFF ISOLATION
100 V+ = 4.5V
50 V+ = 4.5V VCOM = 0.3V 0 +25C
50
ION (nA)
0
IOFF (nA)
+25C
-50
-50 +85C -100 0 1 2 3 VCOM/NX (V) 4 5
-100
+85C
-150 0 1 2 VNX (V) 3 4
FIGURE 19. ON LEAKAGE vs SWITCH VOLTAGE
FIGURE 20. OFF LEAKAGE vs SWITCH VOLTAGE
10
FN6111.3 February 5, 2008
ISL8499 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
200 V+ = 4.2V Sweeping Both Logic Inputs 150
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND (QFN Paddle Connection: To Ground or Float) TRANSISTOR COUNT:
ION (A)
100
228 PROCESS:
50
Si Gate CMOS
0 1 2 VIN1-4 (V) 3 4 5
FIGURE 21. SUPPLY CURRENT vs VLOGIC
11
FN6111.3 February 5, 2008
ISL8499 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 L 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 GAUGE PLANE 0.25(0.010) M BM
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.033 0.0075 0.0035 0.193 0.169 MAX 0.043 0.006 0.037 0.012 0.008 0.201 0.177 MILLIMETERS MIN 0.05 0.85 0.19 0.09 4.90 4.30 MAX 1.10 0.15 0.95 0.30 0.20 5.10 4.50 NOTES 9 3 4 6 7 8o Rev. 1 2/02
A1 0.10(0.004) A2 c
E1 e E L N
e
b 0.10(0.004) M C AM BS
0.026 BSC 0.246 0.020 16 0o 8o 0.256 0.028
0.65 BSC 6.25 0.50 16 0o 6.50 0.70
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
a
12
FN6111.3 February 5, 2008
ISL8499
Package Outline Drawing
L16.3x3
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 4/07
4X 1.5 3.00 A B 6 PIN 1 INDEX AREA 13 12X 0.50 16 6 PIN #1 INDEX AREA
12
1
3.00
1 .50 0 . 15
9
4
(4X)
0.15 8 5 0.10 M C A B + 0.07 4 16X 0.23 - 0.05 16X 0.40 0.10
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C 0 . 90 0.1 BASE PLANE ( 2. 80 TYP )
C
SEATING PLANE 0.08 C 1. 50 ) ( 12X 0 . 5 )
(
SIDE VIEW
( 16X 0 . 23 ) C ( 16X 0 . 60) 0 . 2 REF 5
0 . 00 MIN. 0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
13
FN6111.3 February 5, 2008
ISL8499 Thin Quad Flat No-Lead Plastic Package (TQFN) Thin Micro Lead Frame Plastic Package (TMLFP)
2X A 9 D1 D1/2 6 INDEX AREA N 1 2 3 E1/2 E1 9 2X 0.15 C B 2X 0.15 C A 4X 0 TOP VIEW A2 A / / 0.10 C 0.08 C SEATING PLANE SIDE VIEW NX b 4X P D2 (DATUM B) 4X P 1 (DATUM A) 6 INDEX AREA NX L Ne 8 (Nd-1)Xe REF. BOTTOM VIEW A1 NX b 5 2 3 E2 7 E2/2 8 (Ne-1)Xe REF. D2 2N 5 0.10 M C A B 7 8 NX k A3 A1 B E/2 E 2X 0.15 C B D D/2 0.15 C A
L16.3x3A
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e 1.35 1.35 0.18 MIN 0.70 NOMINAL 0.75 0.20 REF 0.23 3.00 BSC 2.75 BSC 1.50 3.00 BSC 2.75 BSC 1.50 0.50 BSC 0.20 0.30 0.40 16 4 4 0.60 12 0.50 1.65 1.65 0.30 MAX 0.80 0.05 0.80 NOTES 9 9 5, 8 9 7, 8, 10 9 7, 8, 10 8 2 3 3 9 9 Rev. 0 6/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance.
C
9
k L N Nd Ne P
9 CORNER OPTION 4X
SECTION "C-C" C L C L
8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
L1 e 10 L
L1 CC e
10
L
9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Compliant to JEDEC MO-220WEED-2 Issue C, except for the E2 and D2 MAX dimension.
TERMINAL TIP FOR EVEN TERMINAL/SIDE
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN6111.3 February 5, 2008

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